1. Field of the Invention
The present invention relates to recreating a data background to test memory designs. More particularly, the present invention relates to an apparatus and method to test and recreate a data background while testing Static Random Access Memory (SRAM) in a scan based mode with a control system.
2. The Background Art
Memory test algorithms are used to perform high performance test algorithms for SRAM components. More particularly, a variety of methods such as a 2N, 6N or 12N march test algorithm are used to test SRAM components. The 6N march test algorithm uses a specific data background and the complement of the specific data background in a read/write manner which is described here in further detail below.
The 6N march test algorithm is used to test internal RAM data integrity at the CPU manufacturing and debug stage and for field testing and diagnostic testing. The 6N march test consists of six(6) read/write cycles which are accomplished in three passes. Those with ordinary skill in the art will appreciate the six read/write operations identified as:
↑W0, ↑(R0W1), ↓(R1W0R0)
The first operation (↑W0) initializes the memory array by writing a particular data patterns of ones and zeros from lower to higher memory addresses.
The second operation ↑(R0W1) starts from the lower address and reads back the data background deposited in the first pass and writes the complement of the data background to the same location. The complement of the data background verifies that all cells containing a one can store a zero and vice versa.
The third operation ↓(R1W0R0) starts from the higher memory address and reads back the complemented background data deposited in the third operation. After each location is read and verified, the original data is written back to the same memory locations. The operation is concluded by reading back the original background data from the same memory location addresses and verifying the contents of each location.
The 6N test algorithm provides a diagnostic tool for determining memory failure. When performing the 6N test algorithm, the timing for writing the test data background is determined by a scan clock signal which does not operate at the CPU operating speed. By way of example, for a 400 MHz processor, the scan clock generally operates at 50 MHz. The slower scan clock cycle presents a substantial limitation because speed related faults in the SRAM are not tested at its operating speed. Therefore, it would be beneficial to provide a memory test algorithm which can operate at the same clock cycle as the CPU.
Referring to FIG. 1, there is shown a block diagram of a prior art testing system 10 having one input data register 12 which is scannable and used for storing data to be written into SRAM 14. The prior art teaches the use of a single input register 12 in conjunction with the memory test algorithm for conducting SRAM diagnostic testing. The initial data background from the single input register is written into each data line of the SRAM 14. The input data register 12 may be comprised of a plurality of flip-flops and/or macros. A macro comprises a plurality of flip-flops. After the initial data background is written into the data line, the ↑W0 operation is completed. The complement of the ↑W0 operation, i.e. ↑W1, is generated by inverting the initial data background (not shown) and scanning in the inverted data background to the single input register. The operation of the prior art testing apparatus requires special pins (not shown) which can be controlled from an external tester. Since the prior art testing apparatus requires an external tester, the prior art memory test application is limited by tester clock speed.
Referring to FIG. 2, there is shown a block diagram of a prior art testing system 20 having two input data registers 22 and 24 which are written into the SRAM 26. The first input data register 22 and second input data 24 register generate the data background associated with the write operations, ↑W0 and ↑W1, respectively. In operation, the first and second input data registers are then written into the data lines of the SRAM as determined by the 6N memory test algorithm described above. The input data registers for the memory test algorithm may be located on the SRAM 26 itself or in close proximity of the SRAM. Although having two input data registers speeds up the testing algorithm because the complement does not have to be generated, the use of two input registers occupies valuable CPU space.
A xe2x80x9cmacroxe2x80x9d is comprised of a plurality of embedded flip-flops. More particularly, the macro has a scan-in port and scan-out port accessible to the CPU only at the macro boundary flip-flops. By way of example and not of limitation, a macro may consist of four embedded flip-flops which are serially coupled. The first flip-flop would have a scan-in port that is accessible by other components and the fourth flip-flop would have a scan-out port that is accessible by other components. The internal coupling of flops one to four would not be accessible to outside components. The internal coupling for the four flop macro is accomplished by coupling the first flip-flop scan-out port to a scan-in port of a second flip-flop, coupling the second flip-flop scan-out port to the scan-in port of a third flip-flop, coupling the third flip-flop scan-out port to the scan-in port of the fourth flip flop. As previously mentioned, the internal coupling of flops one to four would not be accessible to outside components.
It shall be appreciated by those skilled in the art, that each flip-flop within the macro has receives an associated clocking signal. The clocking signal for each flip flop is determined by a clock controller. The ability to control the clocking signal within each flip-flop with a clock controller is well known in the art.
Macros are predesigned and optimized to improve timing in the CPU. By way of example and not of limitation, a macro may include 4 to 16 flip-flops. If an input data register consists of macros instead of individual flops, the recreation of a data background by feeding the same state back into the individual flip flop is not possible. The inability to feed the same state back to the individual flops in the macro is because there are no scan-in or scan-out ports for flip flops embedded inside the macro.
It would therefore be beneficial to provide an apparatus and method which can recreate a data background for an input register comprising of macro elements in a scan based memory test.
The present invention provides a system and method for re-creating a data background to test memory designs. The system comprises a macro, a first 2-to-1 multiplexer and a second 2-to-1 multiplexer. The macro has an input and output. The first multiplexer is coupled to the macro output and coupled to an inverter which resides between the two first multiplexer inputs. The inverter generates an inverted macro output when enabled. The first 2-to-1 multiplexer receives a control signal which selects the macro output or the inverted macro output to produce a generate a first 2-to-1 multiplexer output. The second multiplexer is coupled to the first mulitplexer output and a normal scan input. The second 2-to-1 multiplexer also receives a select signal which selects between the first multiplexer output and the normal scan input to generate a second 2-to-1 mulitplexer output which is coupled to the macro input.
The present invention also provides a method for recreating a data background to test memory designs for a macro size defined by a plurality of flip-flops. First the macro is initialized with a normal scan input. Selection is then made between a normal shift or an inverted shift. Next, either the normal shift or the inverted shift is performed. The memory is then shifted within the flip-flops according to clocking signals of a shift clock. The number of clocking signals is then compared with the macro size. Finally, the selection between a normal shift or an inverted shift is repeated until the number of clocking signals equals the macro size.